1. Field of the Invention
Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor packaging.
2. Description of Related Art
Power delivery networks (PDNs) have been designed with many individual capacitors to attain the low equivalent series inductance (ESL) needed to manage high frequency impedance resonances. Currently, PDNs may achieve even lower values of ESL through the use of external array capacitors. However, the overall effectiveness of a capacitor is determined by the sum of its ESL and the inductance of the connection between the capacitor and the current source.
Existing techniques using external array capacitors have a number of drawbacks. One technique places the array capacitors on the land-side of the package. This technique uses long, broadly spaced plated through hole (PTH) connections between the capacitors and the silicon die. The PTH connections pass through the large core layer. Due to the long distance between the capacitors and the die, the interconnect inductance becomes significant, resulting in poor ESL. Other techniques use coreless or thin-core technologies, or fine pitch interconnect through the core. These techniques increase the risk of mechanical failure. In addition, the reduction of the interconnect inductance may be inadequate in many applications.